One year after the first release, Simply RISC has updated the S1 Core design to make use of version 1.5 of the Verilog sources contained into the OpenSPARC T1 environment released by Sun Microsystems. The environment has been updated too, and now it contains scripts that support the use of three different "flavors" of the S1 Core: | S1 Core version | Mnemonic | Description | Spartan-3E Area (*) | Virtex-5 Area (**) |
|---|
| S1 Core EE | Elite Edition | Four threads, usual 16K+8K L1 caches | 104K LUTs | 60K LUTs |
|---|
| S1 Core SE | Single-thread Edition | One thread, usual 16K+8K L1 caches | 69K LUTs | 40K LUTs |
|---|
| S1 Core ME | Memory-less Edition | One thread, no L1 caches | 52K LUTs | 37K LUTs |
|---|
(*) Number of 4 input LUTs on Spartan-3E devices, pre-Place-and-Route, obtained with provided push-button script
(**) Number of Slice LUTs on Virtex-5 devices, pre-Place-and-Route, obtained with provided push-button script The numbers above clearly show that the S1 Core will not fit into any existing Spartan device; if you really plan to use FPGA technology you might consider using a Virtex 4 or 5 device with at least 100K LUTs. Learn more...
Go to S1 Core documentation page
Want the design?
Go to the Download Area
|
